1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device having an error correcting system in which a memory block which is one of a plurality of functional blocks in a system LSI utilizes an ECC (Error Correction Code).
2. Description of the Related Art
A so-called system LSI (Large Scale Integrated Circuit) in which a memory, logic circuit and the like are integrated on one system chip to form one system is known. In a system LSI, a plurality of functional blocks (core, macro, IP (Intellectual Property)) such as memory circuits, logic circuits are formed on a semiconductor chip to configure a desired system as a whole.
As a memory block which is one of the IPs is miniaturized, a soft error develops into a serious problem. In order to avoid the soft error problem, it is known to use an error correcting system using ECCs (which is hereinafter referred to as an ECC system). In the ECC system, an error correcting bit (parity bit) is added to data read from a memory cell. An error correcting section in the memory block detects an error of the data bit and the position thereof by use of an error correcting bit and transmits a signal having the error corrected.
Further, a BIST (Built-In Self-Test) block is known as one of the IPs. In the BIST block, a program required for the operation test of the memory block is previously stored. The BIST block automatically makes a test (checking operation) for each memory cell in the memory block according to the program and outputs a test result (for example, whether the memory block is good or faulty).
Also, a BISR (Built-In Self-Repair) block is known as one of the IPs. When the memory block has a repair system (which is hereinafter referred to as a redundancy system) using redundant memory cells, the BISR block determines the position of a faulty memory cell by use of the same method as in the BIST block and controls the memory block so as to replace the faulty memory cell by a redundant memory cell.
A plurality of IPs are provided on the substrate to configure a desired system, but a problem may occur depending on the combination of IPs in some cases.
FIG. 4 schematically shows the configuration when a memory block 1 having the ECC system with the above configuration is combined with a BIST block 2. As shown in FIG. 4, a memory section 11 in the memory block 1 supplies a data bit signal 21 and correction bit signal 22 to an error correcting section 12 according to a control signal 24 from the BIST block 2. The error correcting section 12 detects and corrects an error in the data bit signal 21 and supplies a signal 23 containing a data bit which reflects the error correction to the BIST block 2. The BIST block 2 makes a self-test by use of the signal 23.
However, the BIST block 2 checks the signal 23 which is subjected to error correction (which is hereinafter referred to as ECC correction) by the ECC system by making the combination of FIG. 4. Therefore, the following problems occur.
A case wherein the memory section 11 has a capacity of 1 Mb configured by 1 k word lines×1 k bit lines is explained. It is assumed that the memory is configured so that a group of data bits (which is hereinafter referred to as a word) from 128 memory cells among data of the memory cells connected to one selected word line will be simultaneously output to the exterior of the memory section 11. Further, it is assumed that the number of bits which can be ECC-corrected is one bit for each word (=128 bits) and one bit of the memory section 11 is faulty due to a faulty portion occurring in the manufacturing process. In this case, an error of one bit always occurs in the data bit signal 21 containing the faulty bit, but the error can be ECC-corrected. Therefore, the BIST block 2 determines the memory block 1 as a good product even though a faulty portion occurs in the memory section 11.
However, since the ECC correction cannot be further made for the word containing the error-corrected bit, no error correction is made even if a soft error occurs in the word. When the number of such words is extremely large, the number of words which can be subjected to error correction for the soft error is reduced, and therefore, the memory block 1 becomes less resistant to soft errors as a whole.
Further, as shown in FIG. 5, the same type of problem as described above occurs when a BISR block 4 is used instead of the BIST block 2 by using a memory block 3 having a redundancy system. That is, a faulty memory cell which is ECC-corrected is not dealt with as a memory cell which is to be repaired by the redundancy system as the test result by the BISR block 4. Therefore, the memory block 3 is less resistant to soft errors.